DDR RAM Interface

Data U12
MT41K256M16HA
U5
XAM3359AZCZ100
'DDR_D0' E3M3
'DDR_D1' F7M4
'DDR_D2' F2N1
'DDR_D3' F8N2
'DDR_D4' H3N3
'DDR_D5' H8N4
'DDR_D6' G2P3
'DDR_D7' H7P4
'DDR_D8' D7J1
'DDR_D9' C3K1
'DDR_D10' C8K2
'DDR_D11' C2K3
'DDR_D12' A7K4
'DDR_D13' A2L3
'DDR_D14' B8L4
'DDR_D15' A3M1
Address U12
MT41K256M16HA
U5
XAM3359AZCZ100
'DDR_A0' N3F3
'DDR_A1' P7H1
'DDR_A2' P3E4
'DDR_A3' N2C3
'DDR_A4' P8C2
'DDR_A5' P2B1
'DDR_A6' R8D5
'DDR_A7' R2E2
'DDR_A8' T8D4
'DDR_A9' R3C1
'DDR_A10' L7F4
'DDR_A11' R7F2
'DDR_A12' N7E3
'DDR_A13' T3H3
'DDR_A14' T7H4
'DDR_A15' M7D3
Control U12
MT41K256M16HA
U5
XAM3359AZCZ100
'DDR_BA0' M2C4
'DDR_BA1' N8E1
'DDR_BA2' M3B3
'DDR_DQS0' F3P1
'DDR_DQS1' C7L1
'DDR_RASN' J3G4
'DDR_CASN' K3F1
'DDR_WEN' L3B2
'DDR_CLK' J7D2
'DDR_CLKN' K7D1
'DDR_CKE' K92 U5-G3
'DDR_DQM0' E7M2
'DDR_DQM1' D3J2
'DDR_DQSN0' G3P2
'DDR_DQSN1' B7L2
'DDR_ODT' K1G1
'DDR_RESETN' T2G2 2
'DDR_CSN' L2H2
'DDR_VREF' C124-1 U12-H1 U12-M8 R98-2 C123-1 R100-1 U5-J4
'ZQ' R99-2 U12-L8